1. Field of the Invention
The present invention relates to a power semiconductor device package.
2. Related Background Art
The size and the power loss of a power supply circuit have been reduced along with the development and improvement of the power semiconductor device. The conduction loss of, especially, an AC adapter and the like has been decreased by reducing the on-resistance of a power metal oxide semiconductor field-effect transistor (power MOSFET) which is a switching element mainly used as one of components, and reduction in the power loss of the adapter and the like has been realized.
Since the on-resistance of the power MOSFET is inversely proportional to the area of a chip, use of a power MOSFET chip with a large chip area is required in a power supply circuit with a large rated current. Moreover, the size of a chip which a package can accommodate depends on the size of the package.
Accordingly, the size of a package which accommodates chips of MOSFETs with a large rated current and a low on-resistance is forced to be large.
Here, in a conventional technology, a semiconductor device in which a plurality of semiconductor chips which have different functions from one another are packaged as a laminated structure in order to control increase in the size of the package, to simplify the manufacturing processes, and the like has been proposed, and has become publicly known. In this connection, reference will be made to, for example, Japanese Patent Laid-Open Publication NO. 2002-208673, Japanese Patent Laid-Open Publication NO. 2003-197859, and Japanese Patent Laid-Open Publication NO. 2002-217416.
However, one package accommodates only one semiconductor chip in a conventional semiconductor device package, except a semiconductor device in which a plurality of semiconductor chips with different functions from one another are packaged as a laminated structure.
Since the size of a chip which a package can accommodate depends on the size of the package as described above, the package size, that is, the size of a lead frame is decided, and, then, a maximum chip area which the package can accommodate is decided according to the decision.
Moreover, since the on-resistance of a power MOSFET is inversely proportional to the chip area, a minimum on-resistance is decided by the maximum chip area which the package can accommodate.
On the other hand, the capacity of a power supply circuit has been increased in addition to the reduction of the size and the power loss of a power supply circuit so that the power supply circuit with a large output capacity and a high rated current has been used.
The conduction loss generally becomes large along with the increase in the output capacity and the rated current of the power supply circuit. Accordingly, a power MOSFET chip with small on-resistance, that is, a power MOSFET chip with a large area is required to be used in order to prevent or control the increase in such a conduction loss.
Therefore, a power MOSFET with a large package size has been forced to be used in order to prevent or control the increase in the conduction loss caused by the increase in the output capacity and the rated current of the power supply circuit in a conventional technology.
As a result, it has been difficult to reduce the size of a power supply circuit because the package size of a power MOSFET is increased as the capacity of the power supply circuit becomes large.